The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device having divided and arranged memory blocks and memory block decoder circuits for selecting one memory block that includes a desired memory cell from the plural memory blocks.
An example of a conventional decoder circuit is shown in FIG. 1. As shown in FIG. 1, in the conventional decoding system, first, address signals AiIN and AjIN externally input to a control circuit block 101 are input to an inversion signal generator circuit 103 that is constituted by a circuit including inverters 103i and 103j. The inversion signal generator circuit 103 outputs address signals /AiIN and /AjIN generated from the address signals AiIN and AjIN, and the address signals AiIN and AjiN. The address signals AiIN and AjIN and the address signals AiIN and AjiN are input to a signal driver circuit 104 that is constituted by inverters 105, 106, 107, and 108. The signal driver circuit 104 drives address signals Ai, /Ai, Aj, and /Aj, and transmits the address signals Ai, /Ai, Aj, and /Aj to a desired memory block of plural memory blocks 110, 120, 130, and 140 that are provided in a memory cell area 102. The control circuit block 101 in the conventional semiconductor memory device is constituted by these inversion signal generator circuit 103 and signal driver circuit 104 included therein.
The conventional memory blocks 110, 120, 130, and 140 include decoder circuits BSD with the address signals Ai, /Ai, Aj, and /Aj output from the control circuit block 101 as input to output memory block selection signals for selecting a desired memory block, and memory cell arrays MCA in which plural memory cells are arranged in a matrix form. The decoder circuits BSD and the memory cell arrays MCA in the respective memory blocks are connected by selection signal lines BS 11, BS 12, BS 13, and BS 14 for transmitting the output of the decoder circuits BSD to the memory cell arrays MCA, and the respective decoder circuits BSD and memory cell arrays MCA are disposed apart at nearly the same distance from each other. Conventionally, the decoder circuit BSD that outputs the memory block selection signal for selecting a memory block in which a desired memory block array MCA is provided is constituted by at least an NAND 111 and an inverter 112, for example. That is, two of the four address signals are selectively connected to the decoder circuit included in each memory block.
When selecting a memory block, since levels of one of Ai and /Ai and one of Aj and /Aj are “H”, respectively, one memory block selection signal becomes “H” depending on their combinations, and the corresponding memory block is selected. For example, in the case where both of the address signals AiIN. and AjIN are “L”, the address signals /Ai and /Aj assume “H”, thereby the level of the block selection signal line BS 14 becomes “H” and the memory block 140 are in a selected state. Then, when both of the address signals AiIN and AjIN turn from “L” to “H”, the address signals /Ai and /Aj turn from “H” to “L” and the block selection signal BS 14 turns from “H” to “L”, thereby the memory block 140 comes to assume an unselected state from the selected state. At this time, the address signals Ai and Aj turn from “L” to “H”, and the level of the block selection signal line BS 11 turns from “L” to “H”, thereby the memory block 110 comes to assume the selected state from the unselected state.